1. Field of the Invention
The present invention relates a data transfer control system for executing command transfer, data transfer, and status transfer between modules on the same bus and, more particularly, to a data transfer control system in an input/output controller.
2. Description of the Related Art
An input/output (I/O) controller is generally arranged between an I/O unit, e.g., a disk unit, and a host computer so as to control data transfer therebetween. The I/O controller exchanges transfer information, such as commands, data, and statuses, with the I/O unit. In this case, these pieces of information, such as commands, data, and statuses, are transferred between the I/O controller and the I/O unit through the same bus.
For this reason, in a conventional system, in order to discriminate command transfer, data transfer, and status transfer from each other, a CPU (sub-CPU) in the I/O controller must recognize and control transfer contents every time each piece of information is transferred. When, for example, data is to be written in the I/O unit, the CPU in the I/O controller inquires of the I/O unit whether a command can be received. If the I/O unit is busy, the sub-CPU is kept in a wait state during this period. Upon reception of a response signal, from the I/O unit, representing that the command can be received, the sub-CPU transfers the first byte of the command. The sub-CPU then inquires of the I/O unit whether the second byte of the command can be received. Similarly, if the I/O unit is busy, the sub-CPU is kept in a wait state during this period. Upon reception of a response signal, from the I/O unit, which represents that the second byte of the command can be received, the sub-CPU transfers the second byte of the command to the I/O unit. Subsequently, the sub-CPU transfers the command consisting of a plurality of bytes to the I/O unit in units of bytes in the same procedure as described above. Upon completion of the command transfer, the sub-CPU inquires of the I/O unit whether write data can be received. Upon reception of a response signal representing that the write data can be received, the sub-CPU starts a DMAC (Direct Memory Access Controller) to transfer the write data to the I/O unit. In addition, when status information of the I/O unit is to be read, the sub-CPU must follow the above-described procedure. That is, the sub-CPU in the I/O controller is required to perform cumbersome transfer control. Especially, when a single I/O controller is to control a plurality of different types of I/O units, a single sub-CPU must control command transfer, data transfer, and status transfer with respect to each of the different types of units. That is, the sub-CPU is required to perform data transfer control in accordance with the capacity of each I/O unit. For this reason, the performance of the I/O controller is deteriorated, and it is difficult to efficiently operate all the I/O units.